Numerous memory array configurations require the operation of forcing a current and reading out a voltage during sensing, or forcing a high current to change a status of an array cell as rapidly as possible.
These operations, however, often lack in accuracy because the current control is slowed down by parasitic resistances and capacitances present on a selected path.
Memory devices generally comprise a plurality of memory cells arranged in an array and configured to store data. The memory cells are arranged in a regular array of rows and columns. Memory arrays further comprise a plurality of word lines and a plurality of bit lines. Each word line may be coupled to a row of memory cells, whereas each bit line may be coupled to a column of memory cells. If, for example, a cell array comprises n*m columns of memory cells, the memory device may comprise n*m bit lines. Analogously, if the cell array comprises p rows of memory cells, the memory device may comprise p word lines. The cell array comprising n*m columns of memory cells and p rows of memory cells may then comprise p*n*m memory cells altogether. The word lines and the bit lines are employed to access memory cells for reading, erasing, and programming. Generally, a specific memory cell is read, erased, or programmed by application of specific voltages to the word line and to the bit line coupled to the specific memory cell.
A memory device may furthermore comprise a plurality of sense amplifiers. The sense amplifiers are used to sense the logic levels of the bit lines by amplifying small voltage swings to recognizable logic levels. Therefore, the sense amplifiers are instrumental for read-out of the memory cells.
A memory device may comprise a sense amplifier-bit line multiplexer block which couples the sense amplifiers to the bit lines which are coupled to the columns of memory cells in the cell array. The sense amplifier-bit line multiplexer block is employed to reduce the number of sense amplifiers needed to operate a specific number of columns of memory cells. If, as described above, the cell array comprises n*m columns of memory cells, i.e. n*m bit lines, and a sense amplifier-bit line multiplexer block allowing 1:m multiplexing is employed, n sense amplifiers suffice to operate the n*m bit lines. Each of the n sense amplifiers may be coupled to a data line. Therefore, the memory device may comprise n data lines.
An example conventional memory device with the capacity to store 1 Mbit of data may comprise a cell array comprising 1048576 (=1024×1024) memory cells. The 1048576 memory cells may be arranged in a regular array comprising 512 rows, i.e. 512 word lines, and 2048 columns, i.e. 2048 bit lines. If a sense amplifier-bit line multiplexer block allowing 1:64 multiplexing is employed, 32 sense amplifiers suffice to read out each of the 1048576 memory cells (32 bit data words). If the sense amplifier-bit line multiplexer block allows 1:128 multiplexing, 16 sense amplifiers suffice (16 bit data words).
Due to the structure of memory cell arrays, precise current control in an array cell is difficult. When, for example, a write operation is to be carried out, current control is slowed down by parasitic resistances and capacitances present on a selected path, such as bit line and multiplexer capacitances and equivalent resistances, which results in ineffective current control in an array cell.
For these or other reasons there is a need for an improved method and/or apparatus for controlling current in an array cell.